A67L0636 sram equivalent, 2m x 18- 1m x 36 lvttl pipelined zebl sram.
Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power .
Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write c.
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L1618, A67L0636 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit b.
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